Computer systems use main memory that is typically formed with inexpensive and high density dynamic random access memory (DRAM) chips. When a first row in a DRAM chip is activated, the contents of the memory cells along the first row are read into a page buffer. Subsequent read and write accesses to memory cells in the first row can take place wholly within the page buffer, without accessing the first row again. When a data processor later accesses a second row in the same memory bank, the memory cells along the row are restored in a precharge operation before the other row can be activated. The data processor may later again access the first row in the same memory bank.
Modern DRAM chips typically store one to eight gigabits (Gb) of data using deep sub-micron technology. Because of the high density and small feature size, rows of the memory are so physically close to other rows that the activation of a particular row can upset data stored in adjacent rows by changing the charge on the memory cell capacitors. Typically these upsets are harmless because the memory cells are refreshed periodically. However occasionally some memory access patterns cause certain rows to be activated and precharged so many times before the next refresh cycle that the memory cells in adjacent rows become corrupted and reverse logic state. After being corrupted, the original data is lost and cannot be restored in subsequent refresh cycles.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.